{"id":4232,"date":"2020-09-15T10:39:52","date_gmt":"2020-09-15T10:39:52","guid":{"rendered":"https:\/\/machinalogic.com\/dese_staging1\/?page_id=4232"},"modified":"2020-09-21T17:16:03","modified_gmt":"2020-09-21T17:16:03","slug":"schedule","status":"publish","type":"page","link":"https:\/\/machinalogic.com\/dese_staging1\/schedule\/","title":{"rendered":"Schedule"},"content":{"rendered":"

[vc_row][vc_column][vc_column_text]<\/p>\n

Department of Electronic Systems Engineering (DESE),<\/strong><\/h3>\n

Indian Institute of Science, Bangalore<\/h3>\n

Timetable for October 2020 \u2013 January 2021<\/strong><\/h3>\n

[\/vc_column_text][vc_single_image image=”4603″ img_size=”full”][vc_column_text]<\/p>\n\n\n\n\n\n\n\n\n\n\n\n
E0 284\u00a0 2:1<\/strong><\/td>\nDigital VLSI Circuits<\/strong><\/td>\nChetan Singh Thakur (CST)<\/strong><\/td>\n<\/tr>\n
E2 232\u00a0 2:1<\/strong><\/td>\nTCP\/IP Networking<\/strong><\/td>\nHaresh Dagale (HD), T.V.Prabhakar (TVP), Joy Kuri (JK)<\/strong><\/td>\n<\/tr>\n
E2 243\u00a0 2:1<\/strong><\/td>\nMathematics for Electrical Engineers<\/strong><\/td>\nR. Chandramani Singh (CS), Vittal Rao (RVR)<\/strong><\/td>\n<\/tr>\n
E3 235\u00a0 2:1<\/strong><\/td>\nDesign for Analog Circuits<\/strong><\/td>\nNagakrishna V (NV)<\/strong><\/td>\n<\/tr>\n
E3 245\u00a0 2:1<\/strong><\/td>\nProcessor System Design<\/strong><\/td>\nKuruvilla Varghese (KV)<\/strong><\/td>\n<\/tr>\n
E3 260\u00a0 2:1<\/strong><\/td>\nEmbedded Systems-II<\/strong><\/td>\nHaresh Dagale (HD)<\/strong><\/td>\n<\/tr>\n
E3 262\u00a0 2:1<\/strong><\/td>\nElectronic Systems Packaging<\/strong><\/td>\nUmanand (LU)<\/strong><\/td>\n<\/tr>\n
E3 282\u00a0 3:0<\/strong><\/td>\nBasics of Semiconductor Devices and Technology<\/strong><\/td>\nMayank Shrivastava (MS)<\/strong><\/td>\n<\/tr>\n
E9 253\u00a0 3:1<\/strong><\/td>\nNeural Networks and Learning Systems<\/strong><\/td>\nShayan Srinivasa Garani (SSG)<\/strong><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

[\/vc_column_text][\/vc_column][\/vc_row][vc_row disable_element=”yes”][vc_column][vc_column_text]<\/p>\n

Department of Electronic Systems Engineering (DESE),<\/strong><\/h3>\n

Indian Institute of Science, Bangalore<\/h3>\n

Timetable for October 2020 \u2013 January 2021<\/strong><\/h3>\n

[\/vc_column_text][vc_single_image image=”4603″ img_size=”full”][\/vc_column][vc_column width=”1\/6″][vc_column_text]E0 284\u00a0 2:1
\nE2 232\u00a0 2:1
\nE2 243\u00a0 2:1
\nE3 235\u00a0 2:1
\nE3 245\u00a0 2:1
\nE3 260\u00a0 2:1
\nE3 262\u00a0 2:1
\nE3 282\u00a0 3:0
\nE9 253\u00a0 3:1[\/vc_column_text][\/vc_column][vc_column width=”5\/12″][vc_column_text]Digital VLSI Circuits
\nTCP\/IP Networking
\nMathematics for Electrical Engineers
\nDesign for Analog Circuits
\nProcessor System Design
\nEmbedded Systems-II
\nElectronic Systems Packaging
\nBasics of Semiconductor Devices and Technology
\nNeural Networks and Learning Systems[\/vc_column_text][\/vc_column][vc_column width=”5\/12″][vc_column_text]Chetan Singh Thakur (CST)
\nHaresh Dagale (HD), T.V.Prabhakar (TVP), Joy Kuri (JK)
\nR. Chandramani Singh (CS), Vittal Rao (RVR)
\nNagakrishna V (NV)
\nKuruvilla Varghese (KV)
\nHaresh Dagale (HD)
\nUmanand (LU)
\nMayank Shrivastava (MS)
\nShayan Srinivasa Garani (SSG)[\/vc_column_text][\/vc_column][\/vc_row][vc_row disable_element=”yes”][vc_column][vc_single_image image=”4855″ img_size=”full”][\/vc_column][\/vc_row]<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"

[vc_row][vc_column][vc_column_text] Department of Electronic Systems Engineering (DESE), Indian Institute of Science, Bangalore Timetable for October 2020 \u2013 January 2021 [\/vc_column_text][vc_single_image image=”4603″ img_size=”full”][vc_column_text] E0 284\u00a0 2:1 Digital VLSI Circuits Chetan Singh Thakur (CST) E2 232\u00a0 2:1 TCP\/IP Networking Haresh Dagale (HD), T.V.Prabhakar (TVP), Joy Kuri (JK) E2 243\u00a0 2:1 Mathematics for Electrical Engineers R. Chandramani Singh […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"full-page.php","meta":{"qubely_global_settings":"","qubely_interactions":"","footnotes":""},"class_list":["post-4232","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages\/4232","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/comments?post=4232"}],"version-history":[{"count":4,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages\/4232\/revisions"}],"predecessor-version":[{"id":4856,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages\/4232\/revisions\/4856"}],"wp:attachment":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/media?parent=4232"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}