{"id":4241,"date":"2020-09-15T10:44:12","date_gmt":"2020-09-15T10:44:12","guid":{"rendered":"https:\/\/machinalogic.com\/dese_staging1\/?page_id=4241"},"modified":"2020-09-21T15:28:49","modified_gmt":"2020-09-21T15:28:49","slug":"m-tech-ese","status":"publish","type":"page","link":"https:\/\/machinalogic.com\/dese_staging1\/degree-programs\/m-tech-ese\/","title":{"rendered":"M.Tech. (ESE)"},"content":{"rendered":"<div class=\"wpb-content-wrapper\"><p>[vc_row][vc_column][vc_column_text]<\/p>\n<h3 style=\"text-align: center;\">DEPARTMENT OF ELECTRONIC SYSTEMS ENGINEERING<\/h3>\n<h4 style=\"text-align: center;\">M Tech Programme<\/h4>\n<h3 style=\"text-align: center;\">ELECTRONIC SYSTEMS ENGINEERING <span style=\"color: #ed1c24;\">(2020 Batch onwards)<\/span><\/h3>\n<p>&nbsp;<\/p>\n<p><strong><span style=\"color: #000000;\">Core Courses:\u00a0 15 credits (All courses are compulsory)<\/span><\/strong><\/p>\n<p><span style=\"color: #000000;\"><strong>Electives: 24 Credits <\/strong>(all at 200 level or higher) from the following courses or any other courses listed in the Scheme of Instructions.<\/span><\/p>\n<p><span style=\"color: #000000;\"><strong>Project: 25 Credits<\/strong><\/span><\/p>\n<table style=\"color: #000000; border-collapse: collapse;\" width=\"609\" cellspacing=\"0\" cellpadding=\"0\">\n<tbody>\n<tr style=\"background-color: #0296d3; color: #ffffff; font-size: 18px;\">\n<td colspan=\"4\" width=\"609\"><strong>Duration: 2 Years\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Total Credits: 64<\/strong><\/td>\n<\/tr>\n<tr>\n<td style=\"background-color: #0296d3; color: #ffffff; font-size: 18px;\" colspan=\"4\" width=\"609\"><strong>Core Courses: 15 credits (All courses are compulsory)<\/strong><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E0 284<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/p>\n<p>&nbsp;<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Digital VLSI Circuits<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E2 243<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Mathematics for Electrical Engineers<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 204<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Fundamentals of MOS Analog Integrated Circuits<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 235<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Design for Analog Circuits<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 257<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Embedded System Design<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 239px; height: 47px; border: 1px solid #b2b2b2; padding: 4px; font-size: 18px;\" colspan=\"4\" valign=\"middle\" width=\"609\"><strong>Electives: 24 Credits <\/strong>(all at 200 level or higher) from the following courses or any other courses listed in the Scheme of Instructions.<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E1 201<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Hardware Acceleration and Optimization for Machine Learning<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E1 243<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Digital Controller Design<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E1 261<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Selected Topics in Markov Chains and Optimization<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E2 230<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Network Science and Modeling<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E2 231<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Topics in Statistical Methods<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E2 232<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">TCP-IP Networking<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 200<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">1:2<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Microelectronics Lab<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 225<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Art of Compact Modeling<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 231<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Digital System Design with FPGAs<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 245<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Processor System Design<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 258<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Design for Internet of Things<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 271<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">1:2<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Reliability of Nanoscale Circuits and Systems<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 272<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Advanced ESD Devices, Circuits and Design Methods<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 274<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">1:2<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Design of Power Semiconductor Devices<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 275<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Physics and Design of Transistors<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 276<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Process Technology and System Engineering for Advanced Microsensors and Devices<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 282<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Basics of Semiconductor Devices and Technology<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 290<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Microfabrication Technology and Process for Biology and Medicine<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E3 301<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Special Topics in Nanoelectronics<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E6 202<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Design of Power Converters<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E6 212<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Design and Control of Power Converters and Drives<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E6 222<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">2:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Design of Photovoltaic Systems<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E9 207<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Basics of Signal Processing<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E9 251<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Signal Processing for Data Recoding Channels<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E9 252<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:0<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Aug<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Mathematical Methods and Techniques in Signal Processing<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">E9 253<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">3:1<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Jan<\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Neural Networks and Learning Systems<\/td>\n<\/tr>\n<tr>\n<td style=\"background-color: #0296d3; color: #ffffff; font-size: 18px;\" colspan=\"4\" width=\"609\"><strong>Project: 25 Credits<\/strong><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 72px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">EP 299<\/td>\n<td style=\"width: 43px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">0:25<\/td>\n<td style=\"width: 50px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\"><\/td>\n<td style=\"width: 444px; height: 47px; border: 1px solid #b2b2b2; padding: 4px;\" valign=\"middle\">Dissertation Project<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3><\/h3>\n<p>[\/vc_column_text][\/vc_column][\/vc_row]<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>[vc_row][vc_column][vc_column_text] DEPARTMENT OF ELECTRONIC SYSTEMS ENGINEERING M Tech Programme ELECTRONIC SYSTEMS ENGINEERING (2020 Batch onwards) &nbsp; Core Courses:\u00a0 15 credits (All courses are compulsory) Electives: 24 Credits (all at 200 level or higher) from the following courses or any other courses listed in the Scheme of Instructions. Project: 25 Credits Duration: 2 Years\u00a0 \u00a0 \u00a0 [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":4226,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"full-page.php","meta":{"qubely_global_settings":"","qubely_interactions":"","footnotes":""},"class_list":["post-4241","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages\/4241","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/comments?post=4241"}],"version-history":[{"count":1,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages\/4241\/revisions"}],"predecessor-version":[{"id":4244,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages\/4241\/revisions\/4244"}],"up":[{"embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/pages\/4226"}],"wp:attachment":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/media?parent=4241"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}