{"id":959,"date":"2016-07-05T10:31:17","date_gmt":"2016-07-05T10:31:17","guid":{"rendered":"http:\/\/10.114.1.201\/?p=959"},"modified":"2016-07-05T10:31:17","modified_gmt":"2016-07-05T10:31:17","slug":"micro-electronics-lab","status":"publish","type":"post","link":"https:\/\/machinalogic.com\/dese_staging1\/micro-electronics-lab\/","title":{"rendered":"Micro Electronics Lab"},"content":{"rendered":"<div id=\"dm_content\">\n<section id=\"dm_area_56\" class=\"dm_area dm_page_content\">\n<div class=\"dm_zones clearfix\">\n<div class=\"dm_zone\">\n<div class=\"dm_widgets\">\n<div class=\"dm_widget lab_show\">\n<div class=\"dm_widget_inner\">\n<div class=\"clearfix\">\n<div class=\"markdown\">\n<p class=\"dm_first_p\">This lab treats the topic of digital system design in a integrated manner. FPGA, CPLD, state machine, micro-controllers, DSP and other digital related experiments and projects are handled in this lab.<\/p>\n<p id=\"people-x-18xkuruvilla-varghese-x-19x-x-20xm-krishna-kumar-x-21x-x-22xj-vedavallix-23x-x-24xchandrika-joshix-25x\">PEOPLE: Kuruvilla Varghese , M Krishna Kumar , J Vedavalli, Chandrika Joshi<\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/section>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>This lab treats the topic of digital system design in a integrated manner. FPGA, CPLD, state machine, micro-controllers, DSP and other digital related experiments and projects are handled in this lab. PEOPLE: Kuruvilla Varghese , M Krishna Kumar , J Vedavalli, Chandrika Joshi<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"qubely_global_settings":"","qubely_interactions":"","footnotes":""},"categories":[99],"tags":[],"class_list":["post-959","post","type-post","status-publish","format-standard","hentry","category-labs"],"qubely_featured_image_url":null,"qubely_author":{"display_name":"Admin","author_link":"https:\/\/machinalogic.com\/dese_staging1\/author\/staging_admintest\/"},"qubely_comment":0,"qubely_category":"<a href=\"https:\/\/machinalogic.com\/dese_staging1\/category\/labs\/\" rel=\"category tag\">Labs<\/a>","qubely_excerpt":"This lab treats the topic of digital system design in a integrated manner. FPGA, CPLD, state machine, micro-controllers, DSP and other digital related experiments and projects are handled in this lab. PEOPLE: Kuruvilla Varghese , M Krishna Kumar , J Vedavalli, Chandrika Joshi","jetpack_featured_media_url":"","_links":{"self":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/posts\/959","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/comments?post=959"}],"version-history":[{"count":0,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/posts\/959\/revisions"}],"wp:attachment":[{"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/media?parent=959"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/categories?post=959"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/machinalogic.com\/dese_staging1\/wp-json\/wp\/v2\/tags?post=959"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}